D Esign and V Erification of Fsm Based Timing G Enerator Circuit Using Hdl

As the technology is going on rapidly the major parameters affecting the chip design is area, density and clock speeds. Every digital circuitry [1]. is based on the clock and design of clock for each and every individual module is a bit complex process and so this paper deals with the real time clock in which this clock module can be integrated to various circuits as per their requirement and alarm functionality is also implemented such that this can be helpful in waking up the devices at particular time from the sleep mode to save the power consumption this paper is completely based on the FSM plot[3] also consisting of the counters and the registers this is implemented on the Spartan 3 FPGA board and the complete code coverage report have been generated design have been done using verilog HDL in Xilinx and the verification part have been done in mentor graphics tool